FAST I/O PAD PLACEMENT IN FPGAs
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چکیده
In VLSI physical design, a good placement of logic blocks along with the inputoutput blocks around the boundary of the chip can ensure good quality routing of the nets. Even after proper placement of the logic blocks, a random positioning of input-output blocks can result in inefficient and bad quality routing. Here we propose a placement algorithm GENERATE_PAD_FRAME for input-output blocks, from an entirely new viewpoint. It ensures quality placement of input-output blocks along the pad frame in negligible amount of time. GENERATE_PAD_FRAME can be effectively utilized to generate equally good quality placement in FPGAs much faster. The proposed algorithm is tested on several benchmarks and the experimental results are encouraging.
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